Memory expansion structure in multi-path accessible semiconductor memory device

ABSTRACT

A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2005-127527, filed Dec. 22, 2005, the disclosure of which is herebyincorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

This disclosure relates to a semiconductor memory device, and moreparticularly, to a memory expansion structure in a multi-path accessiblesemiconductor memory device suitable to be employed to a mobilecommunication system.

2. Discussion of Related Art

In general, a semiconductor memory device having multiple access portsis called a multi-port memory. In particular, a memory device having twoaccess ports is called a dual port memory. A typical dual port memory isan image processing video memory having a random access memory (RAM)port accessible in a random sequence and a serial access memory (SAM)port accessible in a serial sequence, which is widely known in thepresent field.

In this disclosure, a dynamic random access memory (DRAM) for readingand writing a shared memory region of a memory cell array made up ofDRAM cells through multiple access ports without the SAM port, unlike aconfiguration of a video memory, will be herein referred to as amulti-path accessible semiconductor memory device in order todistinguish from the multi-port memory.

The use of electronic systems in current societies has expandedubiquitously. In order to insure high-speeds and smooth functionality oroperation in portable electronic systems and electronic appliances, suchas notebook computers, hand-held phones and personal digital assistants(PDAs), for example, manufacturers have used multiprocessor systems asshown in FIG. 1.

Referring to FIG. 1, a first processor 10 is connected with a secondprocessor 12 through a connection line L10. A NOR memory 14 and a firstDRAM 16 are coupled to the first processor 10 through set buses B1through B3. A second DRAM 18 and a NAND memory 20 are coupled to thesecond processor 12 through set buses B4 through B6. The first processor10 may have a modem function for modulating and demodulatingcommunication signals. The second processor 12 may have an applicationfunction for processing communication data or executing games, providingentertainment, and so on. The NOR memory 14 has a NOR cell arraystructure. The NAND memory 20 has a NAND cell array structure. Both arenon-volatile memories having transistor memory cells with floatinggates, and may be used to store data, such as a native code or data ofthe portable appliance that should not be erased even when power isturned off. The first and second DRAMs 16 and 18 act as main memoriesfor the first and second processors, respectively.

However, in the multiprocessor system as in FIG. 1, the DRAMs arecorrespondingly allocated to both the processors, and relativelylow-speed interfaces, such as universal asynchronous receivertransmitter (UART), serial peripheral interface (SPI), static randomaccess memory (SRAM) interfaces. Hence, it is difficult to secure asufficient data transmission speed, size is increased and memorycomponent costs are increased. A scheme for reducing an occupied size,enhancing a transmission speed, and decreasing the number of employedmemories is shown in FIG. 2. A multiprocessor system of FIG. 2 ischaracterized in that one DRAM 17 is connected to first and secondprocessors 10 and 12 through buses B1 and B2 respectively, in contrastto that of FIG. 1. In order for each of the processors to access oneDRAM 17 through two separate paths, two ports are required on the DRAM17. However, the DRAM 17 is generally a device having a singleinput/output path part 16 and a single port PO, as shown in FIG. 3.

FIG. 3 shows a structure of the general DRAM. A memory cell array 1includes first to fourth banks 3, 4, 5 and 6, each of which includes arow decoder 8 and a column decoder 7. An upper input/output senseamplifier and driver 13 is operatively connected with the first bank 3and the third bank 5 through multiplexers 11 and 12. A lowerinput/output sense amplifier and driver 15 is operatively connected withthe second bank 4 and the fourth bank 6 through multiplexers 13 and 14.

For example, when a memory cell in the first bank 3 is selected to readdata stored in the selected memory cell, a process of outputting theread data is as follows. First, the data of the memory cell, which issensed and amplified by a bit line sense amplifier in the cell arrayafter a selected word line is activated, is transmitted to a localinput/output line pair 9 by activation of a corresponding column selectline (CSL). The data transmitted to the local input/out line pair 9 istransmitted to a global input/output line pair 10 by a switchingoperation of a first multiplexer 21, and the second multiplexer 11connected to the global input/output line pair 10 transmits the data ofthe global input/output line pair 10 to the upper input/output senseamplifier and driver 13. The data, which is again sensed and amplifiedby the upper input/output sense amplifier and driver 13, is output to adata output line L5 through the path part 16. Similarly, when datastored in the memory cell of the fourth bank 6 is read, the data isoutput to an output terminal DQ through a multiplexer 24, themultiplexer 14, the lower input/output sense amplifier and driver 15,the path part 16, and the data output line L5 in that order. Thus, theDRAM 1 of FIG. 3 has a structure in which two banks share oneinput/output sense amplifier and driver. In addition, the DRAM 1 is asingle port memory in which the data is input/output through one portPO. Consequently, the DRAM 1 of FIG. 3 may be used in the system of FIG.1, but it is difficult or impossible to be used in the multiprocessorsystem of FIG. 2 due to the structures of the memory bank and port.

Referring to FIG. 4, there is shown a multiprocessor system in which amemory array 35 has first, second and third portions. The first portion33 of the memory array 35 is accessed only by a first processor 70through a port 37, the second portion 31 is accessed only by a secondprocessor 80 through a port 38, and the third portion 32 is accessed byboth the first and second processors 70 and 80. Sizes of the first andsecond portions 33 and 31 of the memory array 35 can be flexibly varieddepending on operation loads of the first and second processors 70 and80. The memory array 35 may be realized as a memory or a disk storage.

When implementing the third portion 32, shared by the first and secondprocessors 70 and 80 in the DRAM structure, several problems may arise.For example, a technique of arranging the memory regions andinput/output sense amplifier in the memory array 35 and controlling aproper read/write path with respect to each port is needed. Furthermore,a processor may require the memory region to be extended. For example, astorage capacity (or a memory capacity) of data that the secondprocessor 80 can read or write in order to provide moving pictures orvarious multimedia needs increasing.

Thus, in the multiprocessor system having at least two processors, thereis a need for a more appropriate solution for sharing the shared memoryregion allocated in the DRAM memory cell array, as well as an improvedmethod of making it possible to additionally extend the capacity ofmemory as much as desired in the system when the specific processorrequires to extend the memory region.

SUMMARY

An embodiment includes a multiprocessor system including a firstprocessor coupled to a first bus, a second processor coupled to a secondbus, a first memory coupled to the first bus and the second bus, and asecond memory coupled to the second bus. The first processor isconfigured to access the first memory through the first bus, and thesecond processor is configured to access the first memory and the secondmemory through the second bus.

Another embodiment includes a multiprocessor system including a firstprocessor coupled to a first bus, a second processor coupled to a secondbus, a first memory coupled to the first bus and the second bus, and atleast one memory receptacle coupled to the second bus. The firstprocessor is configured to access the first memory through the firstbus, and the second processor is configured to access the first memoryand any memory installed in the memory receptacle through the secondbus.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages will become more apparent tothose of ordinary skill in the art by describing embodiments in detailwith reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional multiprocessor system usedin a portable communication device;

FIG. 2 is a block diagram of a multiprocessor system using memoriesaccording to an embodiment;

FIG. 3 is a block diagram illustrating the internal structure of amemory cell array in a conventional DRAM;

FIG. 4 is a block diagram illustrating memory array portions of aconventional multiprocessor system;

FIG. 5 is a block diagram of a multiprocessor system having a multi-pathaccessible DRAM and extended DRAM according to an embodiment;

FIG. 6 is a system block diagram illustrating an example of a memoryextension structure in FIG. 5;

FIG. 7 is a system block diagram illustrating another example of amemory extension structure in FIG. 5; and

FIG. 8 is a detailed circuit diagram of an extended monitoring partillustrated in FIG. 6 or 7.

DETAILED DESCRIPTION

Hereinafter, embodiments of a memory expansion structure in a multi-pathaccessible semiconductor memory device suitable to be used in amultiprocessor system will be described with reference to theaccompanying drawings.

In the following detailed description, numerous specific details ofembodiments are set forth by way of examples with reference to thefigures. However, it should be noted that embodiments may take otherforms and are provided to help those skilled in the art obtain athorough understanding of the scope of the claims. Furthermore,well-known methods, procedures, such as ordinary dynamic random accessmemories and internal circuits have not been described in detail so asnot to cause confusion.

FIG. 5 is a block diagram of a multiprocessor system having a multi-pathaccessible DRAM and extended DRAM according to an embodiment. Themultiprocessor system includes a first processor 10 to perform a firstsetup task, a second processor 12 to perform a second setup task, amulti-path accessible DRAM 17 and a single-path accessible DRAM 19 whichhave memory regions in a memory cell array. Furthermore, themultiprocessor system may include a NOR memory 14 and a NAND memory 20which are connected to the first processor 10 and the second processor12, respectively.

The multi-path accessible DRAM 17 coupled with the first and secondprocessors 10 and 12 through the system buses B1 and B2 respectively,and has at least one shared memory region in the memory cell array anddual access ports. In other words, the multi-path accessible DRAM 17 isa first memory, having at least one shared memory region accessible byboth the first and second processors 10 and 12 through first and secondports that are correspondingly connected to the system buses B1 and B2.

The single-path accessible DRAM 19 is coupled to the second processor 12through the system bus B3, and includes an ordinary single port memoryhaving a dedicated memory region as in FIG. 3. Thus, the single-pathaccessible DRAM 19 is a memory that may increase a memory capacity ofthe second processor 12, and may be accessed only by the secondprocessor 12.

The system bus of the second processor 12 is commonly coupled to portsof the first and second memories 17 and 19, as shown in FIGS. 6 and 7.

There are many uses for a system having the extended memory structure asin FIG. 5. For example, a current portable system such as a portablemultimedia player (PMP) may use such an extended memory structure. Moreand more services are available for PMPs. Such services includesurveying today's share status, watching a movie, playing a game orentertainment, performing Internet surfing, giving an order for productsto an online shopping mall such as an Interpark, exchanging mails,providing navigation based on a road map, etc. when walking along theroad, going to business, making a train or bus journey, going to orleaving the office, enjoying an open-air leisure, going to a skiingground, going fishing, and so on. As a result, a PMP may need morememory than when initially supplied to the user. Thus, the extendedmemory capacity for the second processor 12 may be used to address thisneed.

When the memory regions in the multi-path accessible DRAM 17 of FIG. 5have the same arrangement as the four memory regions 3 through 6 of FIG.3, at least one memory region (e.g. the shared memory region 3) can beaccessed by both the first and second processors 10 and 12. Furthermore,a dual port structure is needed with an additional port PO installed onthe left side as well as the right side illustrated in FIG. 3. Thus,while not shown in FIG. 3, the first memory region 3 becomes a sharedmemory region accessible by both the first and second processors 10 and12 through their own ports, whereas the second to fourth memory regions4, 5 and 6 become dedicated memory regions accessed by the firstprocessor 10 alone.

Each of the four memory regions 3 through 6 may be a bank of the DRAM.Each bank can have a storage capacity of, for instance, 64 Mbit, 128Mbit, 256 Mbit, 512 Mbit, or 1024 Mbit. Memory cells may be arranged inthe memory regions in matrix or row and column form. Each memory cellmay include one access transistor AT and storage capacitor C.

When the first processor 10 accesses the shared memory region throughthe first port, the second processor 12 can access any one of the othermemory regions through the second port at substantially the same time.This multi-path access operation is shown in detail in FIG. 5, but it isimplemented by a control circuit in the memory controlling the accesspath in a proper way.

In one example, the first processor 10 of FIG. 5 can have a modemfunction for modulating and demodulating communication signals or a baseband processing function as a processing task, and the second processor12 can have an application function for processing communication data orexecuting games, displaying video, or other entertainments as aprocessing task. Furthermore, the system bus B1 may be set to 16 bits.The system bus B2 may be the same or may be different. For example, thesystem bus B2 may be set to 16 bits (x16) or 32 bits (x32).

The NAND memory 20 is a non-volatile memory having a NAND cell arraystructure. A NAND memory cell may include a metal oxide semiconductor(MOS) transistor having a floating gate, and thus used as a flash memorycell. The flash memory cell may be used for storing data, such as thenative code and data of a portable appliance that should not be erasedeven when power is turned off. While illustrated to be connected to thefirst processor 10 in the system of FIG. 5, data may be moved from theNAND memory 20 to the NOR memory 14, and vice versa. Then, one of theNAND memory 20 and the NOR memory 14 may be removed when the data istransferred to the other memory.

The system of FIG. 5 may be a portable computing device such as a mobilecommunication device (e.g. a cellular phone), a bidirectional radiocommunication system, a unidirectional pager, a bidirectional pager, apersonal communication system, or a portable computer, a portablemultimedia player, or a portable communication device. However, itshould be understood that the scope and application of the claims arenot limited to these devices.

Furthermore, in the system of FIG. 5, the number of processors can beextended to three or more. The processors of the system can be, forexample, a microprocessor, a central processing unit (CPU), a digitalsignal processor, a microcontroller, a reduced command set computer, acomplex command set computer, or the like. However, it should beunderstood that the scope of the claims is not limited to a particularnumber of processors in the system. Furthermore, the scope of the claimsis not limited to a specific combination of processors, regardless ofwhether the processors are the same or different.

A method in which the second processor 12 accesses (reads or writes) theDRAM 17 and the extended DRAM 19 illustrated in FIG. 5 will be describedwith reference to the attached figures. One of ordinary skill in the artwill understand that the method may be implemented by other systems.

FIG. 6 is a system block diagram illustrating an example of a memoryextension structure in FIG. 5. FIG. 7 is a system block diagramillustrating another example of a memory extension structure in FIG. 5.The extension structure of FIG. 6 employs a scheme in which accesses ofthe first and second memories 17 and 19 are distinguished by the secondprocessor 12 using different commands. Furthermore, the extensionstructure of FIG. 7 employs a scheme in which accesses of the first andsecond memories 17 and 19A are distinguished by the second processor 12using different addresses.

FIG. 8 is a detailed circuit diagram of an extended monitoring partillustrated in FIG. 6 or 7. Referring to FIG. 8, an extended monitoringpart includes an extended detecting section 22 and an extended flagsetting section 14. As illustrated in FIG. 6 or 7, the extendeddetecting section 22 constituting the extended monitoring part may beprovided on a system board such as a printed circuit board, while theextended flag setting section 14 may be installed inside or outside thesecond processor 12. The extended detecting section 22 outputs a logicof a memory extension detecting signal ES to a high level when thesecond memory is mounted. For example, any one of the connector pins ofthe second memory or a user's setup pin (e.g. a pin for adjusting thesetup of the system board when extending a capacity of the memory)connects terminals N1 and N2 installed between a supply voltage VDD anda ground voltage.

The extended flag setting section 14 includes a NAND gate 50, aflip-flop 52, and an extended memory flag buffer 54, and has a wiringstructure as in FIG. 8. When the second memory 19 or 19A is mounted onthe system board, the extended flag setting section 14 sets an extendedmemory flag in a logic low or high state. Thus, the second processor 12can recognize a capacity of the memory which the second processor 12 canaccess by checking a state of the extended memory flag.

As described above in FIG. 6, accesses of the first and second memories17 and 19 can be distinguished by using different commands and in FIG.7, accesses of the first and second memories 17 and 19 can bedistinguished by using different addresses.

In FIG. 6, when a first memory command CMDb1 is applied on command linesCMDb, the first memory 17 is accessed. When a second memory commandCMDb2 is applied, the second memory 19 is accessed. In this case,various lines of signals CLKb, CKEb and ADDRb(m) and data DQS(4) andDQb'S(32) of the second processor 12 are commonly connected to the firstand second memories 17 and 19. The first memory command CMDb1 caninclude a chip select signal CS1 b, a row address strobe signal RASb, acolumn address strobe signal CASb, a write enable signal Web, and anoutput enable signal DQMb. The second memory command CMDb2 can include achip select signal CS2 b, a row address strobe signal RASb, a columnaddress strobe signal CASb, a write enable signal Web, and an outputenable signal DQMb.

In FIG. 7, when a first memory address ADDRb(m) is applied, the firstmemory 17 is accessed. When a second memory address ADDRb(m+1) isapplied, the second memory 19 is accessed. In this case, various linesof signals CLKb, CKEb and ADDRb(m) and data DQS(4) and DQb′S(32) of thesecond processor 12 are commonly connected to the first and secondmemories 17 and 19A. Here, a command CMDb can include a chip selectsignal CS1, a row address strobe signal RASb, a column address strobesignal CASb, a write enable signal Web, and an output enable signalDQMb.

In order to enable the first memory 17 illustrated in FIGS. 5, 6 and 7to be accessed by both the first and second processors 10 and 12,input/output sense amplifier and write drivers can be disposed in theshared memory region of the first memory 17 on left and right sides ofthe cell array respectively, and first and second global multiplexershaving switching operations opposite to each other can be disposed nextto the input/output sense amplifier and write drivers.

Returning to FIGS. 3 and 5 again, the first and second processors 10 and12 makes common use of circuit elements and lines between the ordinaryglobal input/output line pair GIO and GIOB and the memory cell when theaccess operation is performed, and makes independent use of circuitelements and lines associated with input/output from each port to theglobal multiplexer.

More specifically, it should be noted that, as illustrated in FIG. 3,the global input/output line pair GIO and GIOB, the local input/outputline pair LIO and LIOB that is operatively connected to the globalinput/output line pair, the bit line pair BLi and BLBi that isoperatively connected to the local input/output line pair by the columnselect signal CSL, the bit line sense amplifiers that correspond to thebit line pair BLi and BLBi and sense and amplify data of the bit lines,and the memory cells to which the access transistors forming the memorycells on the bit line pair are connected, all of which are disposed inthe shared memory region. The circuitry of FIG. 3 is shared by each ofthe first and second processor 10 and 12 through the first and secondports.

Although, while not described in FIG. 5, it is necessary for the row andcolumn address multiplexers to be installed at front ends of the row andcolumn decoders, and to receive row and column addresses from the portwhose occupation is allowed. Such address multiplexers can be realizedby a clocked complementary metal oxide semiconductor (CMOS) invertercomposed of N-type and P-type MOS transistors.

Referring to FIGS. 3 and 5 together, an operation of the first processor10 accessing the dedicated memory region in the first memory 17 is thesame as that of the ordinary processor accessing the data.

Meanwhile, when the second memory 19 is extended on the system board asin FIG. 6, the second processor 12 recognizes that the second memory 19,the dedicated memory, is extended by checking the state of the extendedmemory flag of the extended flag setting section 14. Here, assuming thatthe second processor 12 accesses the first memory region 3 of the sharedbank in the first memory 17, and that an operation mode at that time isa read operation, the active command CMDb1 and read command are appliedinto the first memory 17 through the second port of the first memory 17to which the second processor 12 is connected. When the row address isapplied, a word line WLi in the shared memory region which the secondprocessor 12 wants to access is activated. When the word line WLi isactivated, the data of the memory cells in which the gates of the accesstransistors AT are connected to the same word line are developed to thecorresponding bit line pair. For example, when the gate of the accesstransistor AT of a memory cell is supplied with a higher voltage than athreshold voltage by a word line boosting operation, a potentialdeveloped to the bit line BLi is varied according to a state of charges(e.g. 1.8 to 3 V in a charged state, and 0 V in an uncharged state)stored in the storage capacitor C. Consequently, a state ofcharge-sharing operation with the bit line in the charged state isdifferent from that in the uncharged state, and such a difference issensed and amplified by the bit line sense amplifier in the array. Forexample, when the potential of the bit line BLi is output to a highlevel, and when the potential of a bit line bar BLBi, a complementarybit line, is output to a low level, a potential of the bit line pair BLiand BLBi is transmitted to the corresponding local input/output linepair LIO and LIOB for the first time when a column gate responding whenthe logic level of the column select signal CSL is high is turned on.

After the word line WLi is activated, and then the data of the memorycell is output to the bit line pair BLi and BLBi as the potential of thehigh or low level, when the column select line is activated by thecolumn decoder for decoding the column address, the potential of the bitline pair BLi and BLBi in the shared memory region is transmitted to thelocal input/output line pair LIO and LIOB as illustrated in FIG. 3. Thedata of the local input/output line pair LIO and LIOB which is output asthe potential level is transmitted to the global input/output line pairGIO and GIOB as illustrated in FIG. 3 when the N-type MOS transistorsconstituting the first multiplexer LIO MUX 21 of FIG. 3 are turned on.Here, a switching signal applied in common to gates of the N-type MOStransistors can be a signal generated by responding to a decoding signaloutput from the row decoder. The data transmitted to the globalinput/output line pair GIO and GIOB is transmitted to the input/outputsense amplifier and driver 13 through the second multiplexer 11 asmentioned above. As illustrated in FIG. 3, the input/output senseamplifier 13 amplifies again the data the level of which is weakened dueto the transmission through the foregoing paths, and transmits theamplified data to an output buffer.

Alternatively, assuming that the second processor 12 accesses thededicated memory region in the second memory 19, and that an operationmode at that time is a read operation, the active commend CMDb2 and readcommand are applied into the second memory 19 through the single port ofthe second memory 19 to which the second processor 12 is connected. Whenthe row address is applied, a word line WLi in the dedicated memoryregion which the second processor 12 wants to access is activated. Whenthe word line WLi is activated, the data of the memory cells in whichthe gate of the access transistor AT is connected to the same word lineare developed to the corresponding bit line pair. The operation ofreading the data in the ordinary DRAM is performed, and thus the data isread to the second processor 12.

In the foregoing embodiments, the case where the one single-path memoryis extended in parallel at the multi-path access memory is taken by wayof example. However, when two or at least three processors are employedto the system, multiple DRAMs may be installed to extend the memory ofthe system board. Although embodiments have been described with DRAMs,other memory types may be used, such as SRAM, non-volatile memory, andso on.

According to the memory and system as set forth above, multipleprocessors can smoothly access the shared memory region allocated in thememory cell array. Thus, the speed of transmitting and processing thedata is improved, and the system is downsized. In addition, when acapacity of memory is increased, the capacity of memory accessible byspecific processors can be easily extended. Hence, the multiprocessorsystem may offer more improvement to users increasing the competitiveadvantage of the system in the marketplace.

While particular embodiments have been described, many modifications,substitutions, changes and equivalents will be apparent to those skilledin the art. For example, in alternative embodiments, the bank or circuitconfiguration and access or extension method in the memory may bevariously modified or changed. It is, therefore, to be understood thatthe appended claims are intended to cover all such modifications andchanges as fall within the scope of the claims.

1. A multiprocessor system, comprising: a first processor coupled to afirst bus; a second processor coupled to a second bus; a first memorycoupled to the first bus and the second bus; and a second memory coupledto the second bus; wherein the first processor is configured to accessthe first memory through the first bus, the second processor isconfigured to access the first memory and the second memory through thesecond bus, and the second memory is separate from the first memory andhas a dedicated memory region that is accessible only by the secondprocessor.
 2. The multiprocessor system of claim 1, wherein: the secondprocessor is configured to selectively access the first memory and thesecond memory according to an address on the second bus.
 3. Themultiprocessor system of claim 1, wherein the second processor isconfigured to selectively access the first memory and the second memoryaccording to a command on the second bus.
 4. The multiprocessor systemof claim 1, further comprising: an extended memory monitoring circuitconfigured to generate an extended memory flag according to whether thesecond memory is installed.
 5. The multiprocessor system of claim 1,further comprising: a third memory coupled to the second processorthrough a third bus, wherein the third memory is a non-volatile memory.6. The multiprocessor system of claim 1, wherein: the first memory isconfigured such that both the first processor and the second processorhave access to at least one common memory cell of the first memory.
 7. Aportable communication system, comprising: a first processor coupled toa first bus and a second bus; a second processor coupled to a third busand a fourth bus; a first non-volatile memory coupled to the firstprocessor through the first bus; a second non-volatile memory coupled tothe second processor through the third bus; a first volatile memorycoupled to the first processor through the second bus and coupled to thesecond processor through the fourth bus; a second volatile memorycoupled to the second processor through the fourth bus; wherein: thesecond processor is configured to selectively access the first volatilememory and the second volatile memory through the fourth bus; and thefirst volatile memory includes a first portion accessible only by thefirst processor, a second portion accessible only by the secondprocessor, and a third portion accessible by both the first processorand the second processor.
 8. The system of claim 7, further comprising:a memory receptacle; and an extended memory monitoring circuitconfigured to generate an extended memory flag according to whether thesecond memory is installed in the memory receptacle.
 9. A multiprocessorsystem, comprising: a first processor coupled to a first bus; a secondprocessor coupled to a second bus; a first memory coupled to the firstbus and the second bus; and at least one memory receptacle coupled tothe second bus; wherein the first processor is configured to access thefirst memory through the first bus, and the second processor isconfigured to access the first memory and any memory installed in thememory receptacle through the second bus.
 10. The multiprocessor systemof claim 1, wherein: the second processor is configured to selectivelyaccess the first memory and any memory installed in the memoryreceptacle according to an address on the second bus.
 11. Themultiprocessor system of claim 1, wherein the second processor isconfigured to selectively access the first memory and any memoryinstalled in the memory receptacle according to a command on the secondbus.
 12. The multiprocessor system of claim 1, further comprising: anextended memory monitoring circuit configured to generate an extendedmemory flag according to whether an additional memory is installed inthe memory receptacle.
 13. The multiprocessor system of claim 1, furthercomprising: a non-volatile memory coupled to the second processorthrough a third bus.
 14. The multiprocessor system of claim 1, wherein:the first memory is configured such that both the first processor andthe second processor have access to at least one common memory cell ofthe first memory.